1. Field of the Invention
The present invention relates to a semiconductor wafer having a surface on which an integrated circuit or the like is to be formed.
2. Description of the Background Art
In the case in which an SOI (Silicon On Insulator) wafer is to be manufactured by bonding a wafer for the support substrate and a wafer for an SOI layer, the SMART CUT method, the ELTRAN method or the like is used. (Referring to the SMART CUT method, for example, see “SMART CUT: A PROMISING NEW SOI MATERIAL TECHNOLOGY” M. BRUEL el al., Proceedings 1995 IEEE International SOI Conference, October 1995, pp. 178-179. Referring to the ELTRAN method, for example, see “HIGH—QUALITY EPITAXIAL LAYER TRANSFER (ELTRAN) BY BOND AND ETCH—BACK OF POROUS Si” N. Sato et al., Proceedings 1995 IEEE International SOI Conference, October 1995, pp. 176-177 and “Water Jet Splitting of Thin Porous Si for ELTRAN” K. Ohmi et al., Extended Abstracts of the 1999 International Conference on Solid State Devices and Materials, Tokyo, 1999, pp. 354-355.)
FIG. 17 is a view showing an example of a conventional SOI wafer. An SOI wafer 400 is a (100) wafer having a (100) plane as a main surface. FIG. 18 is a view showing a section taken along a cutting line W—W in FIG. 17.
As shown in FIGS. 17 and 18, an oxide film layer 2 is provided on one main surface of a wafer 1 for the support substrate formed of a silicon substrate, for example, and an SO layer 3 is formed on the oxide film layer 2 in the SOI wafer 400. The SOI layer 3 and the oxide film layer 2 are formed by bonding a wafer for an SOI layer having an oxide film formed on a main surface to the wafer 1 for the support substrate and then removing a part thereof. The SOI layer 3 and the oxide film layer 2 have almost the same diameters. Both diameters might be slightly varied depending on a manufacturing method.
The SOI layer 3 is provided with a semiconductor device including devices such as MOS (Metal Oxide Semiconductor) transistors TR1 and TR2, a wiring for connecting the devices and the like. Notches 1a and 3a are formed in the wafer 1 for the support substrate and the SOI layer 3 in a direction of a crystal orientation <110>, respectively. Moreover, FIG. 17 also shows crystal orientations <100> and <110> in a wafer plane.
In the conventional SOI wafer, generally, a direction of a channel between a source and a drain of a MOS transistor is provided in parallel with the crystal orientation <110>. The MOS transistors TR1 and TR2 in FIG. 17 are taken as an example. In the MOS transistors TR1 and TR2, designations S, D and G denote a source, a drain and a gate, respectively.
With such an arrangement that the channel direction is parallel with the crystal orientation <100>, however, a transistor characteristic can be changed. More specifically, it is known that such an arrangement as to set the channel direction in parallel with the crystal orientation <100> can enhance current driving force of a P channel MOS transistor by approximately 15%, and furthermore, can also reduce a short channel effect. It is supposed that the current driving force is enhanced because of a greater mobility of a hole of the crystal orientation <100> than that of the crystal orientation <110> and also supposed that the short channel effect is reduced because of a smaller diffusion coefficient of boron of the crystal orientation <100> than that of the crystal orientation <110> (see “Effect of <100> Channel Direction for High Performance SCE Immune pMOSFET with Less Than 0.15 μm Gate Length” H. Sayama et al., IEDM99, pp. 657-660).
In the case in which the channel direction of the MOS transistor is to be provided in parallel with the crystal orientation <100> in the (100) wafer, a direction of the wafer should be rotated by 45 degrees or 135 degrees in order to form a circuit by using a conventional circuit pattern mask, a conventional manufacturing apparatus or the like. In this case, it is desirable that directions of a notch and an orientation flat should be changed from the crystal orientation <110> to the crystal orientation <100> such that a wafer can be exactly applied to the conventional manufacturing apparatus.
However, the simple rotation of the wafer by 45 degrees or 135 degrees hinders the development of a new device in some cases, which will be described below.
In a wafer of a crystal having a diamond structure such as a silicon crystal, a crystal surface {110} or {111} is a cleavage plane. In the case of the (100) wafer, particularly, the crystal surface {110} is the cleavage plane.
In an aspect of the development of a device, a sectional structure of the device formed on a wafer is observed by an electron microscope. In that case, the wafer is often cleaved. If a surface other than the cleavage plane is to be exposed, it is necessary to carry out etching the wafer by using an FIB (Focused Ion Beam) device or the like. Consequently, a great deal of time and labor is required so that a development efficiency is reduced.
When the (100) wafer is simply rotated by 45 degrees or 135 degrees to form, on the surface thereof, a MOS transistor having a channel direction in parallel with the crystal orientation <100>, a structure shown in FIG. 19 is obtained. In FIG. 19, a MOS transistor TR3 is formed on a (100) plane of a wafer 30 on which a notch 30a is provided in a direction of the crystal orientation <100>.
In the case in which the wafer 30 is cleaved, a cleavage plane CL appears in the direction of the crystal orientation <110>. Since the channel direction of the MOS transistor TR3 is provided in parallel with the crystal orientation <100>, a section of the MOS transistor TR3 which is broken obliquely with respect to a direction of a channel or a gate appears. Consequently, the oblique sectional structure to the direction of the channel or the gate is observed, and it is hard to accurately carry out evaluation of a gate width or the like, for example.
Moreover, FIG. 20 shows an example in which a memory cell array device AR having a cell CE such as a memory provided in a matrix is formed on the wafer 30 such that the channel direction is parallel with the crystal orientation <100>. Also in this case, the cleavage plane CL appears in the direction of the crystal orientation <110>. Therefore, the oblique sectional structure to the direction of the channel or the gate is observed. For example, it is hard to accurately evaluate the periodicity of a sectional structure of each cell or the like.
More specifically, if the wafer is simply rotated by 45 degrees or 135 degrees to form the device, it is hard to expose a desirable sectional structure through cleavage. Consequently, the development of a new device is hindered.
Therefore, it is proposed that only a wafer for an SOI layer to be a wafer for the device formation is rotated by 45 degrees and is bonded to a wafer for the support substrate, thereby manufacturing an SOI wafer. As shown in FIG. 21, it is preferable that an SOI wafer 500 should be manufactured by bonding the wafer 30 for an SOI layer of the (100) wafer having the notch 30a in the direction of the crystal orientation <100> to the wafer 1 for the support substrate of the (100) wafer having the notch 1a in the direction of the crystal orientation <110>. Consequently, the wafer can be divided along the cleavage plane of the wafer 1 for the support substrate occupying most of a wafer thickness during the cleavage, and a MOS transistor having a channel direction in parallel with the crystal orientation <100> can be formed.
In this case, the wafer 30 for an SOI layer is provided with the notch 30a in the direction of the crystal orientation <100> and the wafer 1 for the support substrate is provided with the notch 1a in the direction of the crystal orientation <110>. Therefore, it is necessary to prepare two kinds of semiconductor wafers because of a difference in a direction of the notch. Consequently, a manufacturing process is complicated.